FPGA demonstrator of a Programmable ML Inference Accelerator - Martin Foltin - ICRC San Mateo, 2019

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  • #IEEE
  • #Industry Summit
  • #ICRC
  • #IRDS
  • #Rebooting Computing
  • #quantum computing
  • #memristor
  • #storage
  • #FPGA
  • #ASIC
  • #memory
  • #network architecture
  • #NOC
  • #neural network layer
  • #inference bridge
  • #synchronization

Martin Foltin, Hewlett Packard, looks at a collaborative work of the Machine Learning (ML) interference accelerator, including PUMA DPE architecture/software stack, memristor emulation, examples, and future projections.

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  • January 20, 2020

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