Deep learning techniques have achieved great suc- cess on various application areas such as image recognition, speech recognition and natural language processing. However, further increasing the scale of deep learning algorithms makes the use of hardware resources fast increasing and becoming unaffordable. Matrix-vector multiplication is a key computing operation in neural processor design and hence greatly affects the execution efficiency. Memristor crossbar is highly attractive for the implementation of matrix-vector multiplication for its analog storage states, high integration density, and built-in parallel execution. In recent years, many memristor based neural processor design have been implement in VLSI hardware system. The current deign schemes can be generally divided into two different approaches: one is referred to "spiking-based" design whose data are represented by digitalized spikes, and the other one is "level-based" design whose data are represented by analog signals with different amplitude. The performance and robustness of the proposed neural process designs are also evaluated by using the application of digital image recognition in previous work. In this work, we investigate the neural processor design that leverages nano-scale memristor technology. A heuristic flow including device modeling, circuit design, architecture, algorithm is studied.