Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip - Anirudh Jain - ICRC 2018

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  • #IEEE
  • #ICRC
  • #Rebooting Computing
  • #2018
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  • #event
  • #computing
  • #technology
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  • #energy costs
  • #computation
  • #logicmemory
  • #nonvon Neumann
  • #network architecture
  • #graph analytics
  • #sparse data
  • #energy efficiency

Anirudh Jain, Georgia Tech, presents his group’s research findings on tackling the issue of the high energy costs of moving data for computation. Considering logic-memory integration that helps mitigate the von Neumann bottleneck, Jain explains how this has enabled a new class of architectures that help accelerate graph analytics and operations on sparse data streams.

  • Published on
  • March 5, 2019

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