CMP and Hybrid Bonding – Eternal Love or Toxic Relation?

Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley.  More information below.
(29:20 + Q&A) Knut Gottfried, ErzM-Technologies & Fraunhofer ENAS
Summary: As semiconductor feature sizes continue to shrink, traditional geometric scaling is no longer the primary engine of progress. Instead, the drive for greater functionality and performance has led to the development of integrated systems that combine diverse device types – logic, memory, RF, photonics, MEMS, and power electronics – within a single chip or package. This paradigm shift is enabled by heterogeneous integration (HI), widely recognized as the future of semiconductor technology.
Within HI, Chemical Mechanical Planarization (CMP) plays a pivotal role. CMP ensures global planarity and surface finish, supports cross-material compatibility, and delivers planarized, damage-free interconnect layers with high-quality bonding interfaces. It also manages stress and acts as a key enabler for scaling. As hetero integration stacks become increasingly complex, CMP remains the universal planarization toolkit for maintaining yield and precision across diverse material systems. This work focuses on CMP-aware design practices, such as pattern-density balancing and structured dummy-fill insertion, combined with predictive modeling to control dishing, erosion, and topography drift. We establish robust CMP processes tailored for high-volume manufacturing using commercially available consumables (slurries, pads, conditioners). Tunable removal-rate selectivity among deposited materials (e.g., Cu/Ti/SiO?) is achieved through controlled chemistry (oxidizer concentration, chelators, corrosion inhibitors, pH) and mechanical parameters (pad hardness, downforce, platen/carrier speeds, temperature). This approach delivers controlled dishing and minimal erosion, consistent within-die and within-wafer planarity, and hybrid-bonding interfaces with low roughness and defectivity, enabling mass production while reinforcing supply-chain resilience.
For subsequent die preparation, techniques such as laser grooving are employed to clear dicing streets, followed by optional CMP-assisted processing to eliminate edge uplift. These steps are critical for producing clean, damage-free die edges suitable for direct hybrid bonding. Finally, we address different metrology methods as necessary in R&D and volume manufacturing, respectively.
Bio: Knut Gottfried received his Diploma degree in electrical engineering from Chemnitz University of Technology (TUC), Germany, in 1993. Following he worked as research engineer at the Chemnitz University’s Center for Microtechnologies. He was mainly involved in research for advanced interconnect systems. He graduated as Ph.D in 2004. His thesis was about interconnect schemes for SiC-based harsh environment sensor devices. In 2001 Knut took over general responsibility for semiconductor surface preparation technologies at Fraunhofer ENAS. Knut is co-chair of the European CMP- and Wet-Users group and EC chair of the “International Conference on Planarization Technology – ICPT”. He is also founder, co-owner, and CEO of ErzM-Technologies, a company that focusses on customer specific advanced semiconductor process and technology development.

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