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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(30:12 + Q&A) Prof. Choong-Un Kim, University of Texas at Arlington
Summary: As semiconductor devices continue to scale and demand higher performance, advanced packaging technologies have become critical enablers of next-generation systems. A prominent example is heterogeneous integration, where multiple chips with varying form factors and functionalities are assembled using 2D, 2.5D, and 3D architectures. While these packaging innovations have revolutionized device capabilities, they also introduce significant challenges in interconnect reliability and defect detection. Unlike conventional packages, defects in advanced packaging interconnects, such as voids in solder joints, cracks in redistribution layers (RDLs) or through-silicon vias (TSVs), and misaligned Cu/Cu hybrid bonds, are often difficult to isolate without destructive, time-consuming, and resource-intensive methods. To address this, we explore a suite of electrical techniques for non-destructive detection and localization of such defects. This study presents a comprehensive methodology that integrates parametric electrical impedance analysis with machine learning-based classification to identify physical damages in advanced interconnect structures. We investigate common failure modes including micro-cracks, delamination, and void formation, and demonstrate the effectiveness of our approach in detecting latent defects and assessing their impact on long-term reliability. This paper highlights the developed techniques and presents experimental evidence validating their diagnostic potential.
Bio: Dr. Choong-Un Kim is a professor and associate chair of the Department of Materials Science and Engineering at the University of Texas at Arlington. He received his Ph.D. in Materials Science and Engineering from the University of California, Berkeley, and his M.S. and B.S. degrees from Seoul National University. Since joining UT Arlington in 1996, he has initiated numerous research programs focused primarily on reliability issues in chip-level interconnects, including thin-film metals and dielectrics, as well as interconnects used in device packaging. His recent research interests, both experimental and computational, include the mechanisms of interconnect failure due to electromigration, peak current stress, and defective barriers in solder joints and back-end-of-line (BEOL) copper. He is also actively involved in developing fault detection methods and exploring electrochemical deposition techniques for various refractory metals. Dr. Kim’s research on interconnect reliability has been continuously funded by the Semiconductor Research Corporation (SRC) since 2002, along with support from leading microelectronics companies such as Texas Instruments, Intel, and Cisco.
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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(30:12 + Q&A) Prof. Choong-Un Kim, University of Texas at Arlington
Summary: As semiconductor devices continue to scale and demand higher performance, advanced packaging technologies have become critical enablers of next-generation systems. A prominent example is heterogeneous integration, where multiple chips with varying form factors and functionalities are assembled using 2D, 2.5D, and 3D architectures. While these packaging innovations have revolutionized device capabilities ...
