HBM Multi-Die Stacking Challenges with Die to Wafer Hybrid Bonding

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#Hybrid bonding #advanced packaging #metrology #2.5D #3D #die stacking #Cu-Cu #HBM

(21:22 + Q&A) Dr. Jinho An, Applied Materials Inc.
From the First IEEE Hybrid Bonding Symposium
Summary: Discussions on the need for heterogenous integration (HI) of chiplets to overcome the limitations of the Moore’s law and the Von Neumann architecture has been around for a some time now, but adoption of the technology hasn’t yet met expectations partly due to yield concerns and cost. However, the growth in AI and high performance computing technology’s increasing need to accelerate power, performance, area, cost and time to market (PPACtTM) is finally bringing HI into mainstream discussions. One key component to enabling AI is High Bandwidth Memory (HBM). As the name suggests, HBM provides much faster data transfer to allow efficient processing of data required for AI computations, especially for model training. The industry will soon produce 12-high HBM3E with 36GB of memory), but continues to push the boundary of technology to 16-stacks or higher with HBM4. In order to improve the heat dissipation and power efficiency while at the same time maintaining the form factor requirements with higher density chips, the industry is looking to implement hybrid bonding (HB) by directly connecting Cu pads in future HBM nodes. This will be a big innovation compared to the microbumps currently in production. While sub-10 ?pitch die-to-wafer HB (integration of chiplets for HPC) is already in production) the challenges of sub-20 ? pitch HBM is significantly higher due to stacking requirements at much lower temperatures. This presentation will look at generic process flow and discuss the challenges for this upcoming technology.
Bio: Jinho An has been serving as an Account Technologist Director in the Heterogeneous Business Unit of Applied Materials Inc. since 2021. Before Applied, he worked for over 10 years as a process development engineer at Samsung’s Semiconductor R&D Center and Package Development Team working on wafer-level advanced packaging technology and product development including HBM, HD FOWLP and CIS. Jinho An has a B.S. in Inorganic Materials Engineering from Hanyang University and a Ph.D. in Materials Science and Engineering from the University of Texas at Austin.

For other edited  videos from this symposium, visit  https://attend.ieee.org/hbs/?page_id=456

(21:22 + Q&A) Dr. Jinho An, Applied Materials Inc.
From the First IEEE Hybrid Bonding Symposium
Summary: Discussions on the need for heterogenous integration (HI) of chiplets to overcome the limitations of the Moore’s law and the Von Neumann architecture has been around for a some time now, but adoption of the technology hasn’t yet met expectations partly due to yield concerns and cost. However, the growth in AI and high performance computing technology’s increasing need to accelerate power, performance, area, cost ...

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