Novel Metrology for Experimentally Visualizing Hybrid Bonding Induced Thermal Stress
Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(26:00 + Q&A) Jie Li, Purdue University
Summary: Hybrid bonding is rapidly emerging as a critical enabler for advanced 3D integration, including 3D System-on-Chip (3D-SoC) and memory-on-logic stacking. By replacing conventional micro-bump interconnects with direct dielectric-to-dielectric and Cu-to-Cu bonding, this technology delivers finer pitch, lower thermal resistance, and improved electrical performance. Despite these benefits, the stress behavior in Cu/dielectric hybrid bonding structures remains poorly understood, raising concerns for long-term reliability.
In Cu/SiO2 hybrid bonding, the bonding process typically involves two steps: dielectric-dielectric bonding at room temperature, followed by Cu-Cu bonding through high-temperature annealing. During annealing process, the coefficient of thermal expansion (CTE) mismatch between Cu and dielectric materials such as SiO2 induces mechanical stress at the bonded interface. This stress can significantly affect bonding quality, potentially leading to delamination, void formation, or micro-cracks at the interface. Furthermore, under prolonged thermal cycling, these stress concentrations may degrade long-term reliability and device performance.
More critically, the induced stress can propagate to adjacent functional regions, such as through-silicon vias (TSVs) and designated keep-out zones (KOZ). Stress-induced piezoresistive effects in silicon near TSVs can cause mobility variations, shift transistor characteristics and thereby compromising circuit behavior. These phenomena present major reliability concerns for high-performance 3D integrated systems. To date, most investigations have relied on finite element modeling (FEM) to study stress in hybrid bonding. While modeling offers predictive fundamental insights, it cannot fully capture the complex thermo-mechanical interactions during bonding and thermal cycling. A lack of high-resolution experimental metrology has limited the ability to validate simulations or provide direct physical evidence of bonding-induced stress.
This work aims to address the critical gap by developing experimental techniques to directly observe stress distribution in Cu/ SiO2 hybrid bonding structures and to understand its impact on TSVs and KOZ regions. We developed the fabrication process of hybrid bonding structures and proposed a novel Cu/SiO2 hybrid bonding structure that enables Raman signal capture from the inside bonding structures, experimentally characterize the thermal stress in hybrid bonding process, providing calibration and validation to prevailing stress simulation models for hybrid bonding.
Bio: Jie Li is a Ph.D. student in Mechanical Engineering at Purdue University. She earned her bachelor’s degree in 2021 and master’s degree in 2024 from Huazhong University of Science and Technology (HUST). Her recent research focuses on stress and mechanical reliability analysis in hybrid bonding for 3D heterogeneous integration. she is advised by Prof. Tiwei Wei from University of California, Los Angeles.
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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(26:00 + Q&A) Jie Li, Purdue University
Summary: Hybrid bonding is rapidly emerging as a critical enabler for advanced 3D integration, including 3D System-on-Chip (3D-SoC) and memory-on-logic stacking. By replacing conventional micro-bump interconnects with direct dielectric-to-dielectric and Cu-to-Cu bonding, this technology delivers finer pitch, lower thermal resistance, and improved electrical performance. Despite these benefits, the stress behavior in Cu/dielectric hybrid bonding structures remains poorly understood, raising concerns for long-term reliability...
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