Reducing Wafer-to-Wafer Bonding Misalignment to Enable sub 150nm Pitch Hybrid Bonding

Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 22-23, 2026 in Silicon Valley.  More information below.
(15:05 + Q&A) Dr. Christopher Netzband, TEL Technology Center America LLC
Summary: As logic and memory scaling continues to slow, the demand for higher interconnect density and speed has increased in recent years, especially among NAND and DRAM companies. Device performance gains are increasingly being achieved in the back end of line using wafer-to-wafer (W2W) hybrid bonding for SRAM on Logic, 3D NAND, CIS, 3D-SoC, and eventually hybrid bonded CFET architectures. Hybrid bonding is a 3D integration technology to vertically stack heterogeneous wafers with ultra-fine interconnect densities using direct Cu-Cu bonds formed at low temperature (200-400 °C). Traditional packaging technologies like microbumps are only able to scale down to 10 µm pitch, while hybrid bonding can form interconnects directly using Cu pads with 10 µm pitch down to <1 µm pitch, increasing the interconnect density, reducing RC delay, and shrinking package sizes. Previously, Tokyo Electron (TEL) demonstrated industry leading 1 µm and 0.5 µm pitch W2W hybrid bonding with 98% electrical yield across the entire wafer. However, as AI and HPC applications continue to drive interconnect scaling, sub-150 nm pitch hybrid bonding will be needed to reach the required interconnect densities and performance targets. To evaluate sub-150 nm pitch hybrid bonding electrical performance, a 140nm pitch test vehicle was developed. After initial integration, wafers were bonded with the newest generation TEL hybrid bonder and a high-accuracy bonding recipe was developed with residual misalignment <50 nm (figure 1). From this development, 140nm pitch bonding was successfully implemented as demonstrated by Cu grain growth across the interface and void-free bonding. To further understand the contributors to wafer bonding misalignment, the high-accuracy bonding recipe was used on fusion bonded wafers to remove the impact of the bond pad layout. Among three wafers tested, the bonding residuals were <40nm for 99.5% of points tested indicating that the bond pad layout contributes to higher bonding residuals. Additionally, a novel bonding hardware solution to correct the bonding residuals was tested using a calibrated multi-physics wafer bonding simulation capable of predicting the bonding misalignment. The novel bonding hardware solution reduced bonding misalignment from 70 nm M+3? to 14.6 nm M+3? according to the simulation results. These process improvements to reduce the residual misalignment will enable continued pitch reduction for hybrid bonding and the next generation of 3D devices.
Bio: Chris Netzband is a Senior Process Engineer in the 3D Interconnect and Heterogenous Integration group at TEL. He received his BS and MS in Chemistry from Clarkson University and his PhD from SUNY Polytechnic Institute for CMP slurry design. He joined TEL in 2020 to work on improving wafer to wafer hybrid bonding through optimizing the tool, process and integration flow. This work led to the first demonstration of high electrical yield 0.5um pitch hybrid bonding. Currently, he leads wafer to wafer bonding activities at TTCA in Albany NY, developing both hybrid and fusion bonding process to enable new technologies in the semiconductor industry.

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