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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 22-23, 2026 in Silicon Valley. More information below.
(25:12 + Q&A) Thomas Workman, Sr Principal Integration Engineer, Adeia
Summary: Die-to-wafer hybrid bonding has many significant advantages over micro-bump interconnects including a room temperature, low-force bonding process, lower interconnect resistance and capacitance, higher interfacial thermal conductivity, zero standoff, finer interconnect pitches (down to sub-micron), and a simplified process flow. Because of its many advantages, hybrid bonding has achieved acceptance in high volume manufacturing (HVM) of wafer-to-wafer image sensors and single-layer die-to-wafer (D2W) memory on logic devices. In 3-D stacking applications such as High Bandwidth Memory (HBM), hybrid bonding also significantly decreases stack height by eliminating the thickness required for micro-bumps and underfill. However, hybrid bonding has yet to be adopted for multi-die stacking applications. HBM roadmaps show an eventual transition from currently used mass reflow with molded underfill (MR-MUF) or thermal compression using a non-conductive film (TC-NCF) to D2W hybrid bonding within a generation or two. Since total device yield decreases exponentially with the number layers in the stack, minimizing any interconnect-related failures will be a very high priority. Therefore, a clear understanding of stacked D2W hybrid bonding sensitivities to the materials, layer thicknesses, interconnect layout, and fabrication and bonding processes is needed to address these yield concerns. In this presentation, we report on reliability and yield results for an 8-high stack of 50 ?m-thick 8 x 12 mm die with TSV interconnects. Daisy chains of 9400 links spanning the entire 8-layer stack are formed by 15 µm Cu pads connected directly to 5 µm TSVs on a 35 µm pitch. Careful engineering of materials, thicknesses, and assembly processes was needed to create die with minimal warpage, low defectivity, high bond yield, and good reliability.
Bio: Thomas Workman is a Distinguished Engineer at Adeia focusing on Bonding and Integration of hybrid-bond interconnects during his tenure over the past 7 years. He has a BS, MS, & PhD in Materials Science from the California Institute of Technology and more than 20 years of experience in research and development for the semiconductor industry in areas ranging from FEOL to Assembly. He specializes in advancing new technologies from initial concept through to high volume manufacturing.
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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 22-23, 2026 in Silicon Valley. More information below.
(25:12 + Q&A) Thomas Workman, Sr Principal Integration Engineer, Adeia
Summary: Die-to-wafer hybrid bonding has many significant advantages over micro-bump interconnects including a room temperature, low-force bonding process, lower interconnect resistance and capacitance, higher interfacial thermal conductivity, zero standoff, finer interconnect pitches (down to sub-micron), and a simplified process flow ...
