The Impact of Hybrid Bonding on Testing 3D-Stacked Dies

Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley.  More information below.
(28:40 + Q&A) Erik Jan Marinissen, imec
Summary: On the research frontier of 3D-stacked ICs, the traditional use of micro-bump-based vertical interconnects between stacked dies is giving way to hybrid bonding. These are bumpless dielectric bonds with embedded copper, whose pitch—unlike that of micro-bumps—continues to scale down well below 10 um; IMEC has recently demonstrated pitches as small as 250 nm. This talk will discuss some of the challenges and emerging solutions that accompany this transition in high-volume testing for manufacturing defects. As in all semiconductor manufacturing processes, individual dies as well as the subsequent die-stacking operations are prone to defects that must be identified and eliminated through testing before final products reach customers. Most stacked-die manufacturing flows offer multiple test opportunities—commonly referred to as pre-bond test, mid-bond test, post-bond test, and final test. Because numerous testing stages are available, selecting an optimal subset is necessary to keep overall test costs under control. During pre-bond testing—conducted before stacking, when each die is still part of its original wafer—non-bottom dies have only their functional I/Os to stack neighbors as natural test access points. Automatically probing these large arrays of fine-pitch micro-bumps has shown to be feasible down to 40 um pitch. However, recent IMEC research reported (still unpublished) mixed results at 25 um pitch. Since no clear probe technology roadmap exists for pitches below 25 um, it is likely that, for the foreseeable future, for non-bottom dies the functional I/Os cannot be used for probe access. This leaves only two options: (1) skip pre-bond testing altogether, or (2) add dedicated sacrificial probe pads exclusively for pre-bond testing. In practice, performing pre-bond tests is generally advisable, as omitting them can lead to uncontrollable total product costs. After stacking, i.e., during mid-bond, post-bond, and final tests, each die-to-die interconnect must also be tested for manufacturing defects, at least once. This presentation will review the conventional test pattern generation algorithms used in the industry as well as E2 I-TEST, a new approach from imec that achieves higher defect coverage with a reduced number of test patterns. While short defects have historically dominated defect paretos, the advent of hybrid bonding shifts the focus toward open defects, potentially requiring DfT engineers to rethink existing repair mechanisms.
Bio: Erik Jan Marinissen is scientific director at imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs. In addition, he holds the position of visiting researcher at Eindhoven University of Technology (TU/e) in the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale. He holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992) from TU/e. Marinissen has an extensive publication record, co-authoring more than 325 journal and conference papers and co-inventing twenty US/EP patent families.

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