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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(23:18 + Q&AS) Prof. Puneet Gupta, EE Department, UCLA
Summary: As semiconductor integration advances toward 2.5D and 3D chiplet architectures, bonding yield has become a critical determinant of overall system performance and manufacturability. There is limited work on design-usable yield models of hybrid bonding. In this work, we present an extended layout- and process-aware yield modeling framework that integrates the dominant failure mechanisms: (1) defect-induced void formation, (2) stress-driven warpage and debonding, (3) electrostatic discharge induced pad failure, and (2) overlay errors. Our framework incorporates simplified models of void distributions and fracture mechanics to predict local delamination risks, thermal expansion mismatch driven wafer warpage to quantify stress induced peeling and debonding probabilities, and a Monte Carlo–based ESD model to capture first-contact probability distributions and associated pad/IO failure risks. By combining these models, we generate probabilistic maps of failure likelihoods and translates them into yield predictions for specific input design layouts and pad/IO redundancy. This unified methodology enables designers to co-optimize interconnect density, pad placement, and bonding process parameters, providing a systematic approach to maximize bonding yield and reliability in advanced 3D integration.
Bio: Dr.Puneet Gupta is currently a faculty member of the Electrical Engineering Department at UCLA. He received the B.Tech degree in Electrical Engineering from Indian Institute of Technology, Delhi in 2000 and Ph.D. in 2007 from University of California, San Diego. He co-founded Blaze DFM Inc. (acquired by Tela Inc.) in 2004 and served as its product architect until 2007. He has authored over 60 papers, ten U.S. patents, and a book chapter. He is a recipient of NSF CAREER award, ACM/SIGDA Outstanding New Faculty Award, European Design Automation Association Outstanding Dissertation Award and SRC Inventor Recognition Award. He serves as the Program Chair of IEEE DFM&Y Workshop. Dr. Gupta’s research has focused on building high-value bridges across application-architecture-implementation-fabrication interfaces for lowered cost and power, increased yield and improved predictability of integrated circuits and systems. He is a Fellow of the IEEE.
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Presented at the 2026 IEEE Hybrid Bonding Symposium, Jan 21-22, 2026 in Silicon Valley. More information below.
(23:18 + Q&AS) Prof. Puneet Gupta, EE Department, UCLA
Summary: As semiconductor integration advances toward 2.5D and 3D chiplet architectures, bonding yield has become a critical determinant of overall system performance and manufacturability. There is limited work on design-usable yield models of hybrid bonding. In this work, we present an extended layout- and process-aware yield modeling framework that integrates the dominant failure mechanisms ...
