A 40GHz PLL with -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter: RFIC Interactive Forum 2017

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This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-m SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <-73dBc across the whole locking range.

This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-m SiGe:C BiCMOS technology. An in-band phase...

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