A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS: RFIC Interactive Forum 2017

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This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout are optimized for high linearity while maintaining high gain and output power. A capacitance neutralized differential pair with source degeneration inductor for linearity enhancement is discussed. The inductive degeneration technique greatly increases the optimal load impedance, which enables a low loss parallel power combining. The complete PA achieves a measured saturated output power of 18.1dBm with 41.5% power-added efficiency (PAE). With 6 Gb/s QAM-64 signals, the proposed PA achieves an average output power of 8.4dBm and 8.8% PAE, with -25 dBc EVM. All measurements are performed with a fixed bias condition.

This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout...

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