Cart
Create Account
Sign In
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip - Anirudh Jain - ICRC 2018
Anirudh Jain, Georgia Tech, presents his group’s research findings on tackling the issue of the high energy costs of moving data for computation. Considering logic-memory integration that helps mitigate the von Neumann bottleneck, Jain explains how this has enabled a new class of architectures that help accelerate graph analytics and operations on sparse data streams.
Anirudh Jain, Georgia Tech, presents his group’s research findings on tackling the issue of the high energy costs of moving data for computation. Considering logic-memory integration that helps mitigate the von Neumann bottleneck, Jain explains how this has enabled a new class of architectures that help accelerate graph analytics and operations on sparse data streams.
Next Up
00:30:25
00:27:16
00:32:41
