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Accelerating Linear Algebra Kernels On A Massively Parallel Reconfigurable Architecture

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IEEE ICASSP 2020 Virtual Conference May 2020

Much of the recent work on domain-specific architectures has focused on bridging the gap between performance/efficiency and programmability. We consider one such example architecture, Transformer, consisting of light-weight cores interconnected by caches

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Accelerating Linear Algebra Kernels On A Massively Parallel Reconfigurable Architecture

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Much of the recent work on domain-specific architectures has focused on bridging the gap between performance/efficiency and programmability. We consider one such example architecture, Transformer, consisting of light-weight cores interconnected by caches