Analytical Modeling of Thermal Stress in Cu TSVs Incorporating Grain Orientation Anisotropy
(22:54 + Q&A) Zhenliang Pan, UCLA — Through-Silicon Vias (TSVs) are widely used in 3D interconnection technology to increase bandwidth, reduce transmission delay, and accommodate higher interconnect density. With the continuous scaling down of semiconductor devices and the increasing I/O density, TSV dimensions are also required to shrink. When the TSV diameter is reduced to just a few microns or even to the submicron scale, its size becomes comparable to that of a single copper grain after annealing. Because copper exhibits crystalline anisotropy, the grain orientation at the TSV top surface significantly affects the thermal stress distribution there. Therefore, it is necessary to investigate the influence of copper grain orientation. Previous studies have often employed the classical Lame distribution as an analytical solution. However, this approach assumes isotropic constitutive behavior for copper and silicon and thus lacks the ability to capture the anisotropy induced by Cu grain orientation. To systematically examine the impact of grain orientation, we first studied the effect of rotating the copper crystal orientation around the TSV axis on various stress distributions. The results show that such rotations do indeed alter the thermal stress field, but the maximum and minimum stresses at the interface remain constant. Consequently, we further investigated, in the inverse pole figure with respect to the TSV axis, the distribution of the maximum and minimum stresses at the Cu–Si interface. In addition, by varying the axial thickness of the top grain (a key factor for satisfying the single-crystal assumption), FEM simulations and analytical results were compared to determine a critical axial thickness—possibly orientation-dependent—beyond which the analytical solution can reliably substitute FEM within acceptable error tolerance to describe the actual thermal stress distribution. Finally, we demonstrate the potential of applying the analytical solution, combined with stress compensation, for qualitative studies of free-surface TSV annealing scenarios.
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(22:54 + Q&A) Zhenliang Pan, UCLA — Through-Silicon Vias (TSVs) are widely used in 3D interconnection technology to increase bandwidth, reduce transmission delay, and accommodate higher interconnect density. With the continuous scaling down of semiconductor devices and the increasing I/O density … (more)
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