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Trends and Challenges in Interconnect Reliability under 24nm pitch: Copper Extendibility and Subtractive-Ruthenium/Airgap Approaches
(26:07 + Q&A) Huai Huang, PhD, AI Hardware Center, IBM — As semiconductor technology advances toward higher-density integration, interconnect solutions at 24 nm pitch and below face increasing reliability and scaling challenges. This study evaluates material and process options to extend the traditional copper/low-k single or dual damascene interconnect architecture. Copper continues to demonstrate strong potential to support high current density requirements, even at aggressively scaled dimensions. Time-dependent dielectric breakdown (TDDB) performance of low-k dielectrics at sub-10 nm spacing has been explored, with enhanced reliability achieved through the adoption of advanced low-k materials. These next-generation dielectrics offer improved plasma damage resistance, higher tolerance to metal barrier processes, and enhanced mechanical integrity, thereby providing a greater reliability margin for tight metal-to-metal spacing. In parallel, a novel top-via subtractive etch scheme using Ruthenium (Ru) combined with airgap integration is investigated for 18 nm pitch applications. Ruthenium interconnects exhibit superior electromigration resistance, enabling support for higher direct current (DC) density. The airgap formation between Ru lines further reduces parasitic capacitance while maintaining dielectric reliability, demonstrating the potential of this subtractive-Ru/airgap architecture for future technology nodes.
Bio: Huai Huang is the Back-End-of-Line (BEOL) reliability lead engineer in IBM Semiconductor Technology Research and Development, covering advanced node BEOL qualification and future node interconnect reliability research. He joined IBM Research after earning his Ph.D. in Physics from the University of Texas at Austin in 2012. He has been focused on BEOL reliability research and development and most recently on 2nm and beyond BEOL reliability. He has authored or co-authored over 40 publications, and over 40 US patents, with over 1300 citations.
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(26:07 + Q&A) Huai Huang, PhD, AI Hardware Center, IBM — As semiconductor technology advances toward higher-density integration, interconnect solutions at 24 nm pitch and below face increasing reliability and scaling challenges. This study evaluates material and process options to extend the traditional copper/low?k single or dual damascene interconnect architecture. Copper continues to demonstrate… (more)
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