Electronic-Photonic Heterogeneous Integration for Co-Packaged Optics for High Performance Computing

(27:52 + Q&A) Dr. Surya Bhattacharya, A*STAR Institute of Microelectronics (IME)
From the 2024 IEEE Symposium on Reliability for Electronics and Photonics Packaging
Summary: Semiconductor system scaling has been driven by the need to pack increased functionality and performance at lower power and into smaller formfactors. In past decades, system scaling was achieved primarily through CMOS chip scaling. Hyper-scale Data Centres, AI, High Performance Compute, Co-packaged optics, Automotive electronics and 5G/6G/SATCOM applications have driven the industry to adopt multi-chiplet heterogeneous integration packaging to overcome chip-scaling limitations and meet the demanding and diverse needs of Power-Performance-Formfactor-Cost (PPFC) driven semiconductor systems which will soon integrate over a Trillion transistors in a single package. In this paper, we will present the challenges and opportunities that the industry encounters along the path to achieving multi-chiplet Trillion transistor packages for HPC.
Bio: Dr. Surya Bhattacharya is Director and Head of System-in-Package at A*STAR Institute of Microelectronics (IME), Singapore. Over the past 30 years, he has worked on CMOS scaling and Package Scaling at fabless companies, integrated device manufacturer (IDM), and leading Research Institute. At the Institute of Microelectronics, Singapore, Dr. Bhattacharya leads the advanced packaging team to initiate and execute consortia projects to address industry challenges in advanced heterogeneous integration for system scaling. Prior to joining IME, he served as Director of Foundry Engineering at Qualcomm, where he executed technology and manufacturing ramps across multiple foundries around the world. Prior to Qualcomm, he was a Principal Foundry Engineer at Broadcom Corporation. He started his career at Rockwell Semiconductor Systems, Newport Beach, California, where he was Senior Manager for CMOS technology development. Surya has a PhD in Electrical Engineering from the University of Texas at Austin, and B.Tech in Electrical Engineering from the Indian Institute of Technology, Madras.

For additional talks from this REPP, or earlier ones, please visit https://attend.ieee.org/repp