IMS Printed Circuit Board Solder Fatigue Validation

(20:26 + Q&A) Michael Blattau, Ansys — Failure of solder joints from temperature cycling is one of the primary causes of failure in electronics. An understanding of the solder fatigue reliability is important when quantifying overall device reliability. There are several models for predicting solder joint reliability; These are empirical (handbook methods), analytical (ex. Engelmier’s), and numerical (FEA based methods). LEDs have become increasingly used in lighting applications. Their efficiency is desirable for many applications. LEDs, though more efficient than incandescent lighting, still produce a good amount of heat. LED efficiency is still less than forty percent, meaning that sixty percent of the energy is converted to heat. One method of thermal management is using insulated metal substrate (IMS) circuit boards to help conduct heat away from the components. An IMS circuit board consists of metal substrate (typically aluminum or copper), an insulation layer and a copper foil layer. This construction provides excellent thermal management vs. traditional FR-4 circuit boards. The dielectric (insulation layer) on an IMS board provides a thermal conduction path from the LEDs soldered onto the board and electrically isolates the circuit from the substrate. The mechanical properties of the dielectric will greatly influence the solder fatigue reliability of the components mounted on the board. Earlier work has shown a potential correlation between the modulus of the dielectric and the type of attachment scheme with solder fatigue. The following figure shows the different attachment schemes (routing options) used on a PCB.
Bio: Michael Blattau has over 20 years of experience in Electronics Reliability and is currently a Lead Consulting Engineer at Ansys Reliability Engineering Services, where he has helped hundreds of customers in different industry verticals on electronic reliability issues. Prior to working for Ansys he was a Design Engineering Supervisor for over a decade with an embedded computer company. He has knowledge of electronics enclosure design, PCB design/layout, and FEA simulation. He has a master’s degree in electronics packaging.

Edited videos and slides from most of the REPP talks are available at https://attend.ieee.org/repp/?page_id=2110
Join our Dlist to hear about future REPPs: https://attend.ieee.org/repp/?page_id=361
Organized by the IEEE Silicon Valley chapter of the Electronics Packaging Society: https://ieee.org/scveps