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(31:57 + Q&A) Mohanalingam Kathaperumal, Georgia Tech — Advanced packaging for AI and HPC applications is driving demand for large interposers and packages with ultra-high-density interconnects. While wafer-level packaging is limited to 300 mm × 300 mm formats, there is growing interest in panel-level packaging, with panel sizes ranging from 510 mm × 515 mm up to 700 mm × 700 mm. Although organic substrate cores are available in these large formats, their poor dimensional stability severely limits the achievement of high bandwidth density. As a result, several companies-including Absolics, AMD, Intel, Samsung, LG Innotek, and DNP-are actively pursuing glass packaging as an alternative to wafer-level packages. Glass offers highly desirable properties such as exceptional dimensional stability, excellent planarity, superior electrical insulation, large form factor capability, and availability with tailored coefficients of thermal expansion (CTE).
However, the reliability of glass packages remains a key challenge. Mechanical stresses at the interfaces between plated metals and glass can lead to cracking, while plated through-glass vias (TGVs) face risks of delamination and crack propagation during thermal cycling. This talk will address these reliability concerns, exploring root causes, current research efforts, and potential solutions to overcome the challenges in glass packaging.
Bio: Mohanalingam (Mohan) Kathaperumal received his Ph.D. in Chemistry from Indian Institute of Science, Bangalore in 1994. He received his MS and BS degrees in Chemistry from Madras Christian College, Chennai. Following a 4 year stay in Japan as a visiting researcher at KAST and Waseda University, he worked as a research associate/scientist in Chemistry and College of Optics at the University of Arizona. He then joined Nitto Denko Technical Corporation as a research scientist in 2005 and went on to become an associate director, leading a team with a focus on developing waveguide/electrooptic, photorefractive and high-K capacitor materials. Mohan joined as a Senior research scientist at Georgia Tech’s Chemistry department in 2010 and currently he is a senior research engineer at ECE and the 3D Systems Packaging Research Center. His current research interests include advanced materials and processes for packaging with a focus on heterogeneous integration targeting applications in AI/HPC and 5G & beyond. Mohan is also interested in hybrid/photosensitive materials with very large breakdown strength/high temperature stability for energy storage/electronics/photonics applications as well as a special interest in multi-photon based fabrication and imaging studies of complex structures.
Edited videos and slides from most of the REPP talks are available at https://attend.ieee.org/repp/?page_id=2110
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Organized by the IEEE Silicon Valley chapter of the Electronics Packaging Society: https://ieee.org/scveps
(31:57 + Q&A) Mohanalingam Kathaperumal, Georgia Tech — Advanced packaging for AI and HPC applications is driving demand for large interposers and packages with ultra-high-density interconnects. While wafer-level packaging is limited to 300 mm × 300 mm formats, there is growing interest in panel-level packaging, with panel sizes ranging from 510 mm × 515 mm up to 700 mm × 700 mm. Although organic substrate cores… (more)
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