Simulations of Reliability Issues in Microelectronic Packages

(14:42 + Q&A) Jack Kai-chieh Chiang, Purdue University
From the 2024 IEEE Symposium on Reliability for Electronics and Photonics Packaging
Summary: Simulations are presented addressing the issues of Cu wire-bonding interconnections and soldering interconnections. Cu wire-bonding technology is attracting attention in the electronics industry due to its low cost and high electrical and mechanical properties. However, Cu wire bonding is known for its susceptibility to corrosion. This is a new mechano-chemical model that couples corrosion, mechanical response, and fracture. Under high humidity environments, the Cu-rich intermetallic compound (IMC), Cu9Al4, formed at the interface between Cu and Al, undergoes a corrosion degradation process. The IMC expands while undergoing corrosion-inducing interface stresses that nucleate and propagate cracks along the Cu-rich IMC/Cu. The model predicts failure due to corrosion and cracking.
Board-level soldering connects the packages and the boards (PCBs). The mismatch of the coefficient of thermal expansion (CTE) develops thermal stresses that can create recrystallization and fracture in the solder joints. The crystal plasticity model is utilized to understand the recrystallization mechanisms of Sn (tin) in board-level soldering regarding the Sn orientations. Under repetitive temperature cycling, Sn forms recrystallized subgrains, with interfaces weakened due to the precipitation of Sn-Ag-Cu intermetallic compounds. Additionally, the fracture damage model is used to simulate the fracture behavior. The model developed here aims to predict the reliability of Sn solder joints subjected to temperature variations during normal usage.
Bio: Jack Kai-chieh Chiang is a Ph.D. candidate in Mechanical Engineering at Purdue University and was awarded the 2022 Richard C. Chu Memorial Scholarship from his department. He received his M.S. degree from the National Taiwan University and his B.S. degree from the National Tsing Hua University (Taiwan). He is a Semiconductor Research Corporation scholar working on Cu wire-bonding corrosion kinetic and Sn soldering reliability simulations. He was a Co-op Engineer with Nokia for flip-chip advanced semiconductor packaging during his PhD. He also worked at Texas Instruments as a Semiconductor Packaging Engineer before his Ph.D study.

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