A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS: RFIC Interactive Forum

A Low Power High Performance PLL with Temperature Compensated VCO in 65nm CMOS

V. Ravinuthula, S. Finocchiaro; Texas Instruments, USA

This paper presents a fully integrated, low power, low noise Phase-Locked Loop (PLL) implementing a temperature compensated class-C dual-core Voltage Controlled Oscillator (VCO) achieving state of the art phase noise performance. The PLL exhibits low integrated noise enabling the integration of low jitter clocks for high performance data converters supporting GSM requirements for Wireless Infrastructure applications. Implemented in 65 nm CMOS process, the 8 GHz VCO achieves Phase Noise of -140 dBc/Hz at 1 MHz offset measured at 2 GHz output. The PLL exhibits -60 dBc rms noise integrated from 10 kHz to 20 MHz, while maintaining lock for the ambient temperature range -40°C to 105°C, and dissipating ≈ 140 mW