The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power delivery paths between multiple independent power domains. Although the channels are very short and the I/O power can be reduced by an order of magnitude, the huge increase in the transient current in multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multi-die systems. This talk discusses the unique signal and power integrity challenges of chiplet interfaces.
-- mixed technologies/nodes, parallel interconnects, power domains, supply noise, timing jitter ... Dr. Wendem Beyene, for the Santa Clara Valley EPS chapter. Visit www.ieee.org/scveps