Abstract: Drone-borne synthetic aperture radar (SAR) systems are attractive for small and midarea applications due to easy and temporal deployment capability. In this paper, we present a 77GHz drone-borne multistatic frequency-modulated continuous-wave radar transceiver (TRX) which enables multiple drones to cooperate for SAR imaging by wirelessly sharing the reference chirp signal between the drones. The TRX can be configured in the monostatic or multistatic (master/slave) mode by integrated RF switches. The antenna module in this work includes microstrip comb-line and planar Yagi-Uda array antennas for SAR signals and wireless synchronization of the reference chirp signal, respectively. The fabricated radar TRX chip size, including PADs, is 2.20 mm2. From the on-ground measurement, the SAR module detected a metallic object up to 20 meters away with around 11.2-dB SNR in multi-static mode. The TRX consumes 0.92, 1.3 and 0.4 W for monostatic, multistatic master, and multistatic slave modes, respectively.

Abstract: A 1310-nm (O-band) coherent optical receiver (CORX) is demonstrated with a monolithic electronic/photonic integrated circuit (MEPIC) process for short range optical interconnects. The CORX is designed using a 45-nm CMOS SOI photonic process for quadrature phase shift keying (QPSK) and includes I/Q channels that are characterized up to 56 GBaud (112 Gbps) with FECacceptable BER. The receiver achieves 0.73 pJ/bit energy efficiency and, to our knowledge, is the best energy efficiency reported for a coherent optical receiver.

Abstract: This work presents a plastic fiber link in 28-nm CMOS, operating in two adjacent bands centered on 117.5 and 152.5 GHz. Each band supports multi-level (PAM-4) intensity-modulated signaling, which can be detected non-coherently, obviating the need for carrier synchronization. Data rates up to 100 Gb/s are reported for fiber lengths up to 3 m and links up to 11 m are demonstrated at a reduced data rate. A rectification-based detector is proposed to support linear non-coherent demodulation.

Abstract: This paper presents a new concept of passive phase shifters based on manipulating propagation delay through two parallel transmission lines periodically connected via digitally controlled switch networks. The proposed approach enables precise phase control and flat amplitude response across different phase settings. The prototype IC is fabricated in a 45 nm RFSOI process and occupies only 0.033 mm2. The phase control operates with 11.25° steps over 360° at 140 GHz while maintaining an RMS phase error of 1.2°. The insertion loss is 11.5 dB with < ±0.8 dB variation. Among published D-band phase shifters, this work achieves the lowest RMS phase error and reports bi-directional phase control over 360° and calibration-free operation.

Abstract: A dual-band, concurrent 2.4G WLAN and 2.4G narrow band (NB) transmitter (TX) with on-chip feedforward TX-to-TX interference cancellation path for low antenna-to-antenna isolation in IoT devices is proposed. An on-chip cancellation path generates a replica signal of the same magnitude but 180° out-of-phase with respect to the “aggressor” TX signal appeared at the “victim” TX output. With cancellation path properly calibrated, the measured IMD3 product is reduced by 25 dB. Additionally, the maximum output power during concurrent transmission, while meeting the FCC out-of-band emission specification, improves from 10 to 17 dBm across all WLAN channels. With this proposed architecture, the issue of TX-to-TX interference in multi-radio coexistence is finally addressed, opening the door to future high power concurrent multi-band transmitters in reconfigurable IoT devices.

Abstract: This paper presents an 80MHz crystal oscillator with fast-startup capability based on phasealigned clock injection. The instantaneous phase misalignment due to frequency error is detected in real time without interrupting the injection process. The injection clock’s frequency is corrected accordingly and gradually approaches the crystal oscillator’s intrinsic oscillation frequency. Very effective start-up acceleration is demonstrated as benchmarked against ideal injections with zero frequency error. A prototype circuit in 55nm CMOS process achieves 96× and 368× startup time reductions for 3.0V and 1.2V target swings, respectively.

Abstract: This paper presents a Wi-Fi RF transceiver with a 2.4GHz/5GHz/6GHz tri-band switchable design. To support the wide 320MHz channel BW for Wi-Fi 7, the RF LC-tank response and TXLPF drooping are compensated via a proposed TX flatness calibration scheme that flattens the amplitude difference over the 320MHz signal bandwidth and improves the EVM over each sub-carrier. This work also proposes a reset-pulse XO design to significantly reduce the XO phase noise. A VCO pushing compensation and calibration technique is developed to suppress the sensitivity to LDO noise and DC-DC spurs. The integrated PLL RMS jitter is 57.9fs at 7.115GHz. The measured TX EVM floor achieves -42.6dB at 0dBm output power with EHT320 4096-QAM signals. This RF Transceiver occupies 3.74mm2 in 55nm CMOS technology.

Abstract: We present a low-cost dual-stream IF transceiver IC (IFIC) for 5G mm-wave mobile applications. It up/down-converts the baseband signal to an intermediate frequency of 8.4–10 GHz and forms a heterodyne transceiver system together with beamforming ICs to support all FR2 bands. The IFIC features a compact transceiver RF circuitry, low-jitter reconfigurable LO suitable for 256QAM and non-contiguous carrier aggregation, and an integrated MCU in the digital baseband for flexible calibration and control of both transceiver ICs. The IFIC is implemented in 14-nm FinFET and occupies 16.2 mm2. The overall chain IPN measured at 39-GHz band is as low as 114 fs. Thanks to the flexible calibration architecture, digital-pre-distortion (DPD) is demonstrated in TX, which allows for >1 dB of increase in EIRP for both DFT-s- and CP-OFDM signals at EVM of 5.5% at 39-GHz band.

Abstract: This paper presents a high-efficiency transformer-based D-band power amplifier (PA) in 250-nm InP HBT. The PA has a saturated output power of 21 dBm and peak power-added efficiency (PAE) of 23.6%. The small-signal gain and bandwidth are 19.8 dB and 24.4 GHz respectively. Careful design of the biasing networks results in a record OP1dB and associated PAE of 20.4 dBm and 23% respectively. To the authors best knowledge this is the highest PAE ever reported at P1dB for D-band power amplifiers, resulting in record output power and efficiency during modulated measurements up to 20 Gb/s.

Abstract: This work presents a compact double-balanced frequency doubler achieving better than 70% drain and 25% total power efficiency. Complementary NMOS and PMOS devices enable a truly double-balanced frequency doubler. This work’s complementary current reuse structure implements voltage scaling in the device. Voltage scaling enables each device to operate at half the effective supply voltage improving efficiency. The stacked design with inverted NMOS and PMOS positions allows deep class C biasing for an effective VGS of negative 0.5V without on-chip negative voltage generation. These techniques enable a high-efficiency frequency doubler, showing nearly 3× higher drain efficiency and 25% higher total efficiency than previously published frequency doublers. This device offers almost 60% higher efficiency than devices without active second harmonic gain. This work also shows wide-band operation with over 23GHz RF BW and excellent output power of 9.8dBm. Implemented in a commercial 45nm SOI technology, this device presents one of the smallest area consumptions in the literature thanks to the complementary current reuse implementation.