Co-Design of Algorithms & Hardware for DNNs - Vivienne Sze - LPIRC 2019

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#IEEE #LPIRC #2019 #low power #image recognition #competition #MLT #MIT #design #algorithm #hardware #deep neural networks #DNN #deep learning #direct metrics #flexible dataflow #NoC

Vivienne Sze, Microsystems Technology Laboratories at MIT, takes a look at efficiency optimization of algorithm design and considering energy evaluation when building Deep Neural Networks. Sze presents comparisons of adaptations and various examples of existing DNN architecture on different hardware.

Read more at https://rebootingcomputing.ieee.org/lpirc/2019

Vivienne Sze, Microsystems Technology Laboratories at MIT, takes a look at efficiency optimization of algorithm design and considering energy evaluation when building Deep Neural Networks. Sze presents comparisons of adaptations and various examples of existing DNN architecture on different hardware.

September 12, 2019

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