An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS: RFIC Interactive Forum

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An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS

Liheng Lou, Bo Chen, Kai Tang, Supeng Liu, Yuanjin Zheng; Nanyang Technological University, Singapore

The paper presents an ultra-wideband, low-power frequency synthesizer for Ku-band FMCW radars. This ADPLL-based frequency synthesizer generates chirps with configurable rate from 0.4 to 3.2GHz/ms, up to 2GHz bandwidth in triangle or sawtooth mode. Adaptive loop bandwidth is adopted to reduce variations of the loop tracking characteristic during ramping under different chirp rate, by which, a low frequency RMS error of ~179kHz is achieved for the chirp rate below 2GHz/ms. Fabricated in a 65nm CMOS, the synthesizer generates a wideband chirp from 13.8GHz to 15.8GHz, and consumes 36.3mW, featuring state of the art performance

An Ultra-Wideband Low-Power ADPLL Chirp Synthesizer with Adaptive Loop Bandwidth in 65nm CMOS

Liheng Lou, Bo Chen, Kai Tang, Supeng Liu, Yuanjin Zheng; Nanyang Technological University, Singapore

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