The Future of AI Requires Efficient Power Delivery inside the Processor - APEC 2024

The development of IVRs (Integrated Voltage Regulators) has been an effort now lasting for over 20 years, but never before it has become such an important focus as it is today. AI processors are approaching currents of 1,000 A and heterogeneous integration is bringing a variety of demanding loads, from traditional logic and memory to optical interfaces, inside the package. As already recognized by many thought leaders, energy efficiency is the ultimate metric to achieve the vision of sustainable advanced computing, which will support the next societal and economic transformation. Co-development of all sub-systems to minimize “Joules/Flop” is the new Moore’s Law to enter the Petaflop era, and power management is one of the most critical enablers to achieve the objective.

Francesco Carobolante explores solutions to advance technology leadership and competitiveness as a Director of Corporate Strategy & Ventures at Intel,. In his previous positions as VP Engineering at Qualcomm and Sr Director at Fairchild and STMicroelectronics, he developed many industry "firsts" in power management, WPT, signal processing, RF, digital audio and many others. Carobolante holds MSEE degrees from University of Padova and UCLA and has authored over 90 issued patents; he is Sr. Member of IEEE, co-chair of IEEE Future Networks Energy Efficiency Working Group, Member of IEEE Heterogeneous Integration Roadmap, and Member of the Steering and Technical Committees for several IEEE PELS and PSMA initiatives, including PwrSoC and EnerHarv.