Verilog to Digital Chip - An Introduction

In this presentation, we present some steps of designing basic digital chips from Verilog. We consider elementary Boolean gates and circuits and give the design steps so that the chips can be made using the open-source Tiny Tapeout procedure. We consider the following example, F = AB + C’. 

• Steps using Cadence to Verilog to GDS file – quick overview
• Steps using efabless from Verilog to GDS file – quick overview
• Sending chip for fabrication – MOSIS, TinyTapeout