CIRCUIT DESIGN USING FINFETS

1515 views
Download
  • Share

After HKMG, FinFETs are a powerful yet disruptive technology to enable continuous scaling following Moore’s

law. The disruptive nature arises from both the 3D structure and the quantization on width choice. FinFETs require

new design skills to trade-off among PPA (power-performance-area) and to conduct circuit-process

co-optimization. Salient advantages of FinFETs include: increased driving capability per footprint area, better

control on short-channel effect, subthreshold slope, and less requirement on channel doping. Thus, threshold

voltage can be reduced, which enables a reduction in supply voltage and thus power consumption or increase

of performance speed.

The tutorial will focus on critical issues of FinFET design: It starts with a crisp comparison of planar vs. 3D FinFET

devices and the associated SPICE modeling. Next, logic design is presented, including effects on standard cells,

I/O circuitry, and ESD. Then, the subjects of SRAM and analog/mixed-signal design are treated in detail. Digital

chip-level design that requires methodology enhancement and new CAD tool features are carefully discussed.

The tutorial will enable CMOS designers to systematically comprehend circuit design using FinFETs.

Instructor: Bing Sheu

Bing Sheu obtained a BSEE from National Taiwan University, and Ph.D. degree from UC Berkeley. He taught at

USC during 1985 – 1998, and was promoted to Full Professor in 1997. He moved to industry in 1999 and joined

TSMC in 2006 as Director at R&D Design and Technology Platform. He was the original Creator of the BSIM

(Berkeley Short-channel IGFET Model). He served as Editor-in-Chief of IEEE Transactions on VLSI Systems (1997

& 98), Founding Editor-in-Chief of IEEE Transactions on Multimedia (1998 & 99), and President of IEEE Circuits

and Systems Society (2000). He is an IEEE Fellow, a recipient of IEEE Guillemin-Cauer Award in 1997, and IEEE

CAS Society Meritorious Service Award in 2004. He currently serves on the Program Committees of ISSCC and

VLSI Circuits Symposium.

The tutorial will focus on critical issues of FinFET design: It starts with a crisp comparison of planar vs. 3D FinFET

devices and the associated SPICE modeling. Next, logic design is presented, including effects on standard cells,

I/O circuitry, and ESD. Then, the subjects of SRAM and analog/mixed-signal design are treated in detail. Digital

chip-level design that requires methodology enhancement and new CAD tool features are carefully discussed.

The tutorial will enable CMOS designers to systematically comprehend circuit design using FinFETs.

Advertisment

Advertisment