ON-CHIP VOLTAGE AND TIMING DIAGNOSTIC CIRCUITS

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Instructor: Frank O’Mahony

Frank O’Mahony leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro, Oregon. He

develops the first wireline I/O circuits for each new CMOS process technology. From 2003 until 2011 he was a

member of the Signaling Research group in Intel’s Circuit Research Lab. His research interests at Intel include

high-speed and low-power data links, clock generation and distribution, and on-die measurement techniques.

Frank received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University,

Stanford, CA, in 1997, 2000, and 2004, respectively. He received the 2003 Jack Kilby Award for Outstanding

Student Paper at ISSCC for his work on standing-wave oscillators. Frank is a member of the ISSCC Wireline

Subcommittee and an Associate Editor for TCAS-I.

This tutorial introduces a set of practical and powerful techniques and circuits to observe and characterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and noise limitations associated with bringing signals off-chip to be measured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity, I/O eye margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter. Because the measurements are fully integrated, the rest of the system can be automatically adapted based on these metrics in a stand-alone manner. Best of all, many of these techniques leverage existing circuitry and are highly digital.

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