SOC DESIGN METHODOLOGY FOR IMPROVED ROBUSTNESS

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Instructor: Anthony M. Hill

Anthony Hill is a Distinguished Member of Technical Staff for Texas Instruments, Dallas, TX. He leads the

technology, physical implementation, and signoff team for TI’s Multi-Core Systems Business Unit. He has been

involved in the execution of 6 generations of complex SOCs and cores from 180nm to 28nm focused on

communications infrastructure and high-performance embedded computing centered around TI’s C6X DSP

family. He joined TI in 1996 after taking his BSEE from Oklahoma State University in 1992, and MSEE and PhD

from the University of Illinois Urbana-Champaign in 1993 and 1996. He is currently serving on the ISSCC

High-Performance Digital subcommittee.

A holistic approach to power and performance attainment for semi-custom SoC designs is required to properly optimize future generation devices. We will cover novel techniques which tie SoC development together from micro-architecture to design signoff using examples from production SoCs. We discuss SoC clocking structures, local vs. distributed dividers, real-world implementation of clock-gating and data-driven clock power reduction. This is tied to design signoff, specifically, margin and signoff corner requirements including use of statistical STA. We will discuss how to select process corners and the type of outlier circuits which must be comprehended. Other novel areas of SoC optimization are considered including repeater insertion and repeater circuits for low power, auto-extraction and use of regularity in place and route, and SRAM power optimization.

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