A Scalable Architecture for Integrating Spin Qubits with Cryogenic Electronics

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#quantum computing #quantum error correction #scalable architecture #cryogenic electronics #spin qubits

(20:24) René Otten, Forschungszentrum Jülich GmbH -- Presentation from 2023 Workshop on Quantum Computing: Devices, Cryogenic Electronics and Packaging (QC-DCEP) ... 
Summary: Spin Qubits are quickly emerging as one of the most promising platforms for a scalable quantum computing system, mainly due to increasing qubit numbers and fidelities compatible with quantum error correction. However, scaling beyond lab-scale systems to millions of qubits remains an open challenge. In this talk, I will elaborate on our plan to tackle this problem using a highly scalable architecture and cryogenic electronics. Our approach increases the native pitch of spin qubits from the nm regime to tens of um with minimal wiring overhead, matching the qubit pitch with the space requirements of cryogenic control electronics. I present details on our architecture, which is based coherent shuttling of electrons and how it can reduce the number of necessary control signals per area. To emphasize the validity of our approach, I will present the results of EPR-pair separation in a shuttling device recently measured in our lab.
Subsequently, I will briefly review recent results using a cryogenic CMOS-DAC to generate bias voltages for spin qubits, and the use of discrete heterojunction bipolar transistors (HBTs) for readout. For the first, we successfully operated a custom-designed DAC on the mixing chamber of our cryostat next to the qubit device. Extrapolating the DAC’s performance, we find that we should be able to push the power consumption for DC voltage generation to less than 100 pW/ch. For the HBTs, I will discuss our efforts to minimize the power consumption of these discrete transistors used for spin qubit readout, building on work previously developed by other research groups. I will conclude the talk with our plan on how to integrate spin-qubits with cryogenic electronics in a single QPU, touching on issues such as wiring concepts, thermal design, and packaging.
René Otten is at the JARA Institute for Quantum Information, Forschungszentrum Jülich GmbH and RWTH Aachen University, Aachen, Germany. He received his doctoral, M.Sc., and B.Sc degrees in physics from RWTH Aachen University, Germany, in 2023, 2017, and 2015 respectively. His dissertation at a joint institute with the Forschungszentrum Jülich GmbH focused on integrating semiconductor spin qubits with electronics at cryogenic temperatures. He is currently building up a group on cryogenic electronics for quantum computation as part of the JARA Institute for Quantum Information and RWTH Aachen University. In 2022, he also joined the local start-up ARQUE Systems building scalable quantum computers based on spins in semiconductors. His research focuses on scalable quantum computing systems based on semiconductors. This includes CMOS electronics in cryogenic environments and the integration of spin qubits in semiconductor quantum dots with cryogenic electronics.

Additional videos from the QC-DCEP Workhop can be accessed at https://attend.ieee.org/qc-dcep.

(20:24) René Otten, Forschungszentrum Jülich GmbH -- Presentation from 2023 Workshop on Quantum Computing: Devices, Cryogenic Electronics and Packaging (QC-DCEP) ... 
Summary: Spin Qubits are quickly emerging as one of the most promising platforms for a scalable quantum computing system, mainly due to increasing qubit numbers and fidelities compatible with quantum error correction. However, scaling beyond lab-scale systems to millions of qubits remains an open challenge. In this talk, I will elaborate on our plan to tackle this problem using a highly scalable architecture and cryogenic electronics ...

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