Thermal Management Challenges in Cryogenic System Integration: Spin Qubit Biasing with a CMOS DAC at mK Temperature

(15:50 + Q&A) Lea Schreckenberg, Forschungszentrum Jülich GmbH -- Presentation from 2023 Workshop on Quantum Computing: Devices, Cryogenic Electronics and Packaging (QC-DCEP) ... 
Summary: To pave the way of integrating millions of qubits to run advanced algorithms on a universal quantum computer, a scalable control and read out of these qubits is crucial for the overall system. Due to the wiring in state-of-the-art dilution refrigerators (DR), the systems’ scalability with room temperature electronics is strictly limited. From our perspective, the approach of placing cryogenic electronics on the intermediate 4K stage of a DR is shifting the wiring bottleneck from room temperature to 4K without tackling the challenge at hand of wiring towards the mixing chamber (MC). Having integrated circuits (ICs) operating next to the qubits at mK temperatures could represent a solution to solve the scalability challenge. However, the development of innovative strategies for cryogenic circuits becomes essential.
Based on this, the talk will give an overview about the recent activities of our custom designed CMOS demonstrator in form of a scalable, fully integrated, eight channel Bias-DAC designed in a 65-nm bulk CMOS technology co-integrated at the MC plate with different gate defined spin qubit devices. We present the DC bias of a single electron transistor as well as a single and double quantum dot bias of one of the qubit devices with the DACs power consumption of about 20 uW. This is framed by a detailed review of different setup iterations with respect to power dissipation and the resulting temperature dependencies. The usage of an interposer as a future System in Package (SiP) chip carrier shows new challenges for a quantum processor unit (QPU) underlined by measurement results with different materials and assemblies. Thus, we emphasize the systems requirement to connect the IC and the qubit device electrically while thermally isolating them from
the carrier.
Lea Schreckenberg is a postgraduate researcher working at the Central Institute of Engineering, Electronics and Analytics – Electronic Systems (ZEA-2) at the research center Jülich. She received her masters degree in electrical engineering at the University of Applied Sciences Aachen in 2020. She is focusing on the integration of scalable control electronics with spin qubit devices for quantum computing for her doctoral research, with interests in cryogenic characterization and thermal management.

Additional videos from the QC-DCEP Workhop can be accessed at https://attend.ieee.org/qc-dcep.