Advanced Packaging Overview: Architectures, Challenges, and Technical Solutions

(22:38 + Q&A) Xiaorong Xiong and Jason Zhang, Intel Corp.
From the 2024 IEEE Symposium on Reliability for Electronics and Photonics Packaging
Summary: Moore’s law has been guiding the industry to achieve higher performance and lower cost mainly through transistor technology advancement for almost 60 years. The latest challenge of computing power requires more core, more caches, more memory, more I/Os, therefore better power delivery and thermal management efficiency, as well as better signal integrity, which result in much large die size and package form factor, which put significant cost and customer enabling challenges. Given these key product challenges, advance package technologies thrive to enable Si disaggregation and heterogenous integration.
Intel invented three disruptive technologies: Embedded Multi-die Interconnect Bridge (EMIB) family, 3D Foveros family and Intel newly announced Glass Core technology, which enable higher I/Os/mm, higher signal integrity and low cost. This presentation will focus the two technologies of EMIB and 3D Foveros: technology descriptions and overview, technology challenges and opportunities including process, material, reliability and etc.
Bio: Xiaorong Xiong is a principal engineer at Intel. From 2005 to 2021, she worked as package process development engineer in different areas such as chip attach, TCB, ball attach, component attach, wire bonding etc for client, hybrid modem, and latest data center EMIB products. From 2021, she has been working with external OSAT to develop package solutions for Intel products including WiFi, thunderbolt, etc; and to drive digitalization and efficiency improvements for the outsourced manufacturing. She holds a Ph.D degree in electrical engineering from University of Washington, Seattle.
Bio: Jason Zhang is a Senior principal engineer who has worked Intel package assembly R&D for 27 years. He is currently responsible for external advanced packages, including 2.3D, 2.5D and 3D technologies, to service Intel products and IFS products. In this role, Jason works with Business Units to understand product requirements, and define the external technology roadmap to meet Intel product needs. His previous role was pathfinding of Intel future package technologies, including Embedded Multi-die Interconnect Bridge (EMIB) family and Foveros technology family. He had many key roles besides of the pathfinding in his 27 year Intel career. He led the R&D of Second Level (SLI) interconnection to control package warpage, and to provide customer surface mount (SMT) solutions to ensure high SMT yield and meet solider joint reliability. Jason was the platform manager to develop package technology of huge size Products for high end servers and tinny size products for hand hold devices. He led his package R&D team develop novel integrated solutions for then world-largest lidded BGA package for Intel. Jason also co-managed Horizonal Integration Department to support fundamental characterizations and innovations across all assembly modules and yield/LYA. Jason received his Ph.D degree from the Department of Materials Science and Engineering in The University of Pennsylvania. He received his Bachelor Degree and Master Degree from the Department of Materials Science and Engineering in Tianjin University. Jason has more than 30 publications and hold nine patents.

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