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SIMULATION TECHNIQUES FOR DATA CONVERTER DESIGN
Instructor: Shanthi Pavan
Shanthi Pavan obtained the B.Tech. degree in Electronics and Communication Engineering from the
Indian Institute of Technology, Madras in 1995 and the D.Sc. from Columbia University, New York in
1999. He is now a Professor of Electrical Engineering at the Indian Institute of Technology, Madras. His
research interests are in the areas of high-speed analog circuit design and signal processing.
Dr. Pavan is the recipient of the IEEE Circuits and Systems Society Darlington Best Paper Award (2009),
the Swarnajayanthi Fellowship (2010, from the Government of India), the Young Faculty Recognition
Award from IIT Madras (2009, for excellence in teaching), the Technomentor Award from the India
Semiconductor Association (2010) and the Young Engineer Award from the Indian National Academy
of Engineering (2006). He is the Deputy Editor-in-Chief of the IEEE Transactions on Circuits and Systems:
Part I - Regular Papers, and serves on the Data Converter Committee of the ISSCC.
ADC and DAC designers spend much time running long simulations that verify functionality and performance of their designs. Some converter designs contain many nominally identical cells (e.g. flash ADCs and current steering DACs). In some others the ratio of the sampling and signal frequencies is very high (oversampling ADCs). This tutorial, targeted at non-experts, will showcase some simulation techniques that are used in ADC/DAC designs. A brief overview of various architectures and examples involving behavioural and SPICE-like simulators will be given.
