On-Shoring The Next Generation Of Advanced Packaging

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#heterogeneous integration #FOWLP #bonding #substrates #chiplets #domestic USA sourcing

(37:45 + Q&A)  Charles Woychik, Ph.D., SkyWater Technology  -- HI, FOWLP, cu-to-cu bonding, 2.5D & 3D, chiplets, domestic sourcing, investments ... 
Summary: Electronics packaging is the critical enabling technology to achieve 3D heterogeneous integration (HI). The core HI advanced packaging technologies are Si-interposers, Cu-to-Cu (CtC) and fan-out wafer-level packaging (FOWLP). In this presentation, an overview of these technologies will be presented along with their respective technical challenges.
For Si-interposers, as the body size increases and the thickness decreases, it becomes challenging to assemble the topside die using conventional solder and underfill assembly methods for die pitches less than 10um. CtC technology is a low temperature, wafer-to-wafer, and die-to-wafer hybrid bonding method, to reliably assemble die having submicron pitches. A reliable die-to-wafer assembly platform with submicron pitch capability will enable widespread chip disaggregation and chiplet architecture innovation. CtC offers bonding throughput comparable to mass reflow flip chip assembly. The bonding takes place at room temperature in an ambient environment in a class 1000 cleanroom. A low-temperature batch anneal after bonding results in a solid Cu-Cu interconnect with no solder or underfill.
FOWLP is rapidly gaining popularity for advanced packaging applications because it offers a substrate-less package, which enables shorter interconnections that provides for improved electrical performance and lower cost. There are two approaches for FOWLP. Chips-first is a process whereby the chips are attached to a temporary carrier and molded to create a reconstituted wafer, which then has a buildup-layered structure deposited on the surface of the chips to create an RDL layer to interconnect the I/O pads on the chip to the ball grid array (BGA) pads. In the chips-last approach, the RDL is created first and then the chips are assembled. The benefit of this approach is that the RDL structure can be tested prior to chip attach, to avoid placing a good die on a bad site. Again, there are numerous technical challenges, such as test methods to get known good die (KGD), accommodating finer lines and spaces (<2um) and migrating this technology from wafers to panels. Recently SkyWater Technology and Deca Technologies signed a technology transfer and licensing agreement. The agreement establishes the first high-volume FOWLP capability in the U.S. to bring proven solutions for single and multi-die packaging and advanced heterogeneous capability for chiplets through 2.5D and 3D integration using M-Series™ fan-out technology and Adaptive Patterning®.

Bio: Charles G. Woychik is the Senior Director of Advanced Packaging Platforms at SkyWater Technology in Kissimmee, FL. Previously he was the Chief Scientist at i3 Microsystems in St. Petersburg, FL. He was the Senior Director of 3D Technology at Invensas Corporation and was a Senior Scientist at GE’s Global Research Center. He began his career at IBM Endicott, NY where he held both engineering and managerial positions. His area of expertise is materials and processes for electronics packaging. He holds a Doctorate and Master of Science degree in Materials Science and Engineering from Carnegie-Mellon University. His Bachelor of Science degree in Metallurgical Engineering is from the University of Wisconsin-Madison. Chuck has presented at numerous conferences and has many publications. He has 123 issued US issued patents to his credit.

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(37:45 + Q&A)  Charles Woychik, Ph.D., SkyWater Technology  -- HI, FOWLP, cu-to-cu bonding, 2.5D & 3D, chiplets, domestic sourcing, investments ... 
Summary: Electronics packaging is the critical enabling technology to achieve 3D heterogeneous integration (HI). The core HI advanced packaging technologies ...

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