Superconducting qubits are a leading candidate for constructing a large-scale quantum processor due to their lithographic scalability and relatively long coherence times. 3D qubit packaging, enabling the integration of more chips with greater functionality, higher I/O counts, and smaller pad pitches –- while maintaining qubit coherence –- is critical for scalable computing architecture. In this talk, I will present a microbump-based assembly approach to produce three-tier stacks with a qubit chip on the top, superconducting multi-chip-module (SMCM) on the bottom, and an interposer chip with superconducting through-silicon vias (TSVs) in the middle. I will discuss our work developing a double bump-bonding process to create the qubit-interposer-SMCM stack, focusing on electrical characterization, alignment accuracy, spacing and co-planarity.
This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), the Defense Advanced Research Projects Agency (DARPA), and by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract No. FA8702-15-D-0001.
44:10 plus Q&A; microbump-based assembly, three-tier stacks, superconducting indium solder bumps, silicon interposer, alignment accuracy, co-planarity. Lincoln Lab project on packaging for quantum devices.