YAP: A Yield Model for Advanced Packaging

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Submitted by mky0726@hanyan… on Sat, 02/01/2025 - 00:14

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"In Session 4: Hybrid Bonding Metrology, a different presentation has been uploaded instead of the 'Yield Modeling for Hybrid Bonding' video. Could you please check and update it if possible?"

#Hybrid bonding #advanced packaging #metrology #2.5D #3D #die stacking #Cu-Cu

(21:20 + Q&A) Prof. Puneet Gupta, Electrical and Computer Engineering Department, University of California
From the First IEEE Hybrid Bonding Symposium 
Summary: Three-dimensional integration technologies present a promising path forward for extending Moore’s law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets at high interconnect density. This paper introduces YAP, an assembly yield model for wafer-to-wafer (W2W) and die-to-wafer (D2W) hybrid bonding. The model accounts for key failure mechanisms that contribute to yield loss, including overlay errors, particle defects, excessive wafer surface roughness and Cu density, and Cu recess variations. YAP enables the co-optimization of packaging technologies, assembly design rules, and overall design methodologies. We also develop an open-source yield simulator and compare the accuracy of the near-analytical yield model with the simulation results.
Bio: Puneet Gupta received the B.Tech. degree in electrical engineering from the Indian Institute of Technology Delhi, New Delhi, India, in 2000, and the Ph.D. degree from the University of California at San Diego, San Diego, in 2007. He is currently a Faculty Member with the Electrical and Computer Engineering Department, University of California at Los Angeles. He Co-Founded Blaze DFM Inc., Sunnyvale, CA, USA, in 2004 and served as its Product Architect until 2007. He has authored over 200 papers, 18 U.S. patents, a book and two book chapters in the areas of design-technology co-optimization as well as variability/reliability aware architectures. Dr. Gupta is an IEEE Fellow and was a recipient of the NSF CAREER Award, the ACM/SIGDA Outstanding New Faculty Award, SRC Inventor Recognition Award, and the IBM Faculty Award. He has led the multi-university IMPACT+ Center which focused on future semiconductor technologies. He currently leads the System Benchmarking theme within the SRC CHIMES JUMP 2.0 center.

For other edited  videos from this symposium, visit  https://attend.ieee.org/hbs/?page_id=456

(21:20 + Q&A) Prof. Puneet Gupta, Electrical and Computer Engineering Department, University of California
From the First IEEE Hybrid Bonding Symposium 
Summary: Three-dimensional integration technologies present a promising path forward for extending Moore’s law, facilitating high-density interconnects between chips and supporting multi-tier architectural designs. Cu-Cu hybrid bonding has emerged as a favored technique for the integration of chiplets at high interconnect density. This paper introduces YAP, an assembly yield model for wafer-to-wafer (W2W) and die-to-wafer (D2W) hybrid bonding....

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