Cryogenic CMOS Technologies for Quantum Computing Systems

(37:38 + Q&A) Dr. Alexander Grill, imec
From the 2024 IEEE Symposium on Reliability for Electronics and Photonics Packaging
Summary: Large-scale quantum computers are not only contenders to break limits of CMOS computing but also have the potential to massively boost fundamental research in fields such as cryptography, computational chemistry, and material science. Integrating CMOS circuits and qubits at cryogenic temperatures is one of the key challenges to mitigate wiring constraints and ensure signal integrity to enable up-scaling of quantum computers. Interfaces between classical and quantum circuits need to maintain ultra-low power consumption together with very low noise figures; therefore it is necessary to develop on-chip solutions with ultra-low power consumption and optimized (noise) performance. Lowering the supply voltage for cryogenic circuits is the most common approach to lower power consumption, hence the margins for device reliability and variability of CMOS devices at cryogenic temperatures is a topic of great interest.
In my talk I will highlight the importance of understanding device physics at cryogenic temperatures to enable CMOS circuits being specifically optimized for cryogenic temperatures. Furthermore, I will discuss the importance of defects to the temperature scaling of low-frequency noise, the role of band-tails and how to model charge trapping kinetics at cryogenic temperatures. I will end my talk by introducing two integrated cryo-CMOS circuits designed at imec used to overcome the measurement bottleneck typically observed in qubit and cryo-CMOS characterization.
Bio: Alexander Grill studied Microelectronics at TU Vienna, where he received his master’s degree in 2013 and his doctoral degree in 2018. He is currently working as a principle researcher for cryogenic CMOS electronics at imec, Leuven. His main scientific interests are characterization and modeling of semiconductor devices at cryogenic temperatures with a special focus on charge trapping, charge noise, and reliability. His current focus is studying time-zero variability and device degradation to enable the design of low-noise, low-power circuits at cryogenic temperatures down to the mK regime. He has authored and coauthored more than 80 journal articles and conference contributions. Additionally, he is principle investigator of the European project ARCTIC, which brings together 36 institutions from Europe and Canada to push forward materials, circuits, and applications for cryogenic CMOS electronics.

For additional talks from this REPP, or earlier ones, please visit https://attend.ieee.org/repp
See also the Quantum Computing: Devices, Cryogenic Electronics and Packaging Symposium: https://attend.ieee.org/qc-dcep