Co-Packaged Optics: Heterogeneous Integration of Photonic ICs and Electronic ICs

(43:06 + Q&A) Dr. John H Lau, Unimicron Technology, IEEE Fellow, and EPS Distinguished Lecturer  -- vs SiPhotonics, photonic ICs, optical transceiver, form factors, performance, bridge vs interposer, billion transistors, AI engines, glass substrates ...
Summary: Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost.
Outline:   — Silicon Photonics   — Data Centers   — Optical Transceivers   — Optical Engine (OE) and Electrical Engine (EE)   — OBO (on-board optics)   — NPO (near-board optics)   — CPO (co-packaged optics) — Integration of the PIC and EIC — 2D Heterogeneous Integration of PIC and EIC   — 2D Heterogeneous Integration of ASIC Switch, PIC and EIC   — 2D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges — 3D Heterogeneous Integration of PIC and EIC   — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC   — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges   — Heterogeneous Integration of ASIC Switch, PIC and EIC on Glass Substrate.
Bio: Dr. John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 as the principal investigator), 52 issued and pending US patents (31 as the principal inventor), and 23 textbooks (all are the first author). John is an elected IEEE Fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

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