Thermal Challenges and Advanced Cooling Opportunities for 2.5D and 3D High Performance Computing

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#Thermal design #heat extraction #2.5D #3D #advanced packaging #heterogeneous integration

(47:16 + Q&A) Herman Oprins, Principal MTS & R&D Team Leader, imec  -- heterogeneous system scaling, logic+memory+optical, backside power, thermal design, advanced cooling ...
Summary: 3D integration technology enables heterogeneous system scaling by offering higher I/O densities, shorter interconnect lengths, higher bandwidth and smaller form factors compared to 2D packaging solutions. In recent years, many products have been released taking advantage of this technology to combine logic, memory and imaging and/or optical components into 3D stacked die, or 2.5D interposer configurations. Due to the vertical integration of thinned silicon chips, the strong thermal coupling between the tiers in the 3D stack, and the difficulty to remove heat from within the 3D die stack, thermal management is one of the major challenges of 3D integration technology. The incorporation of 3DIC and co-packaged optics on 2.5D interposer architectures to boost the compute throughput, has further complicated the cooling challenge.
   In this talk, the thermal impact of the recent scaling trends in 3D die and wafer stacking and CPO, including hybrid bonding, backside power delivery, and BEOL scaling will be discussed. Furthermore, the thermal opportunities of 3D functional partitioning and advanced liquid cooling solutions, to enable 2.5D HPC applications of multiple kW, will be addressed.

Bio: Herman Oprins is a Principal Member of Technical staff and R&D team leader at imec, where he is leading the thermal modeling and characterization team. He holds a M.Sc and Ph.D in Mechanical Engineering from the K.U.Leuven, Belgium. He joined imec in 2003, where he has been involved in the thermal experimental characterization, thermal modeling and thermal management solutions ranging from device level, over chip level to the system level. His activities cover a wide range of electronic applications including advanced chip packages, 3D system integration, Si photonics, CMOS device scaling, back-end of line interconnect, GaN power transistors, photovoltaic modules and microfluidics.

For additional videos, plus new technical talks, from the Central Indiana EPS Chapter, please visit r4.ieee.org/cis-eps

(47:16 + Q&A) Herman Oprins, Principal MTS & R&D Team Leader, imec  -- heterogeneous system scaling, logic+memory+optical, backside power, thermal design, advanced cooling ...
Summary: 3D integration technology enables heterogeneous system scaling by offering higher I/O densities, shorter interconnect lengths, higher bandwidth and smaller form factors compared to 2D packaging solutions. In recent years, many products have been released taking advantage of this technology to combine logic, memory and imaging and/or optical components into 3D stacked die, or 2.5D interposer configurations. Due to the vertical integration of thinned silicon chips, the strong thermal coupling between the tiers in the 3D stack, and the difficulty to remove heat from within the 3D die stack ...

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