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(56:50 + Q&A) -- multi-core microprocessors, 3D stacking, multiple power rails, current density, energy limits, system-in-package ... Kaladhar Radhakrishnan, Intel Fellow and a Power Delivery Architect, Intel.
Power delivery requirements for the early microprocessors were fairly rudimentary due to the relatively low power levels. However, several decades of exponential scaling powered by Moore’s law has greatly increased the power requirements and the complexity of the power delivery schemes. The breakdown in Dennard scaling in the mid-2000s has ushered in the multi-core era which has increased the number of cores and the power consumption in microprocessors. The steady growth in the power levels and the number of power rails in high performance microprocessors has increased the power delivery challenges. New trends like heterogeneous integration and 3D-stacking through advanced packaging technologies further exacerbate the power delivery problem.
Integrated Voltage Regulators (IVR) have emerged as a key power delivery technology to address these challenges. There are a number of IVR schemes implemented on-die ranging from the simple power gate to fully integrated switching regulators. The key performance vectors to judge the quality of the IVR are conversion efficiency, current density, load regulation and configurability. We will look at some of the popular IVR solutions that are being used today and project the performance required to keep pace with the expected demand for future microprocessors. We will conclude by looking at additional solution vectors such as PowerVia that are being pursued to address these power delivery challenges.
Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He has played a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise are in integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award. He has authored four book chapters, over 40 technical papers in peer reviewed journals, and has been awarded 35 US patents. Kaladhar joined Intel in 2000 after he received his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign.
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(56:50 + Q&A) -- multi-core microprocessors, 3D stacking, multiple power rails, current density, energy limits, system-in-package ... Kaladhar Radhakrishnan, Intel Fellow and a Power Delivery Architect, Intel.
Power delivery requirements for the early microprocessors were fairly rudimentary due to the relatively low power levels. However, several decades of exponential scaling powered by Moore’s law has greatly increased the power requirements and the complexity of the power delivery schemes. The breakdown in Dennard scaling in the mid-2000s has ushered in the multi-core era which has increased the number of cores ...
